View FT24C02A-5LR-T_4915428.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

fremont micro devices ft24c02a ? 2009 fremont micro devices inc. ds3011b-p age 1 two-wire serial eeprom 2k (8-bit wide) features ? low voltage and low power operations: ? ft24c02a: vcc = 1.8v to 5.5v, industrial temperature range (-40 to 85 ) . ? two versions of ft24c02a: ? ft24c02a-5xx: low cost with 5 valid pins. suitable for most application except those with more than one eeprom on the same iic bus. details in the ?device addressing? section. ? ft24c02a-uxx: 8 valid pins suitable for all application. ? maximum standby current < 1a (typically 0.02 a and 0.06a @ 1.8v and 5.5v respectively). ? 16 bytes page write mode. ? partial page write operation allowed. ? internally organized: 256 8 (2k). ? standard 2-wire bi-directional serial interface. ? schmitt trigger, filtered inputs for noise protection. ? self-timed programming cycle (5ms maximum). ? 1 mhz (5v), 400 khz (1.8v, 2.5v, 2.7v) compatibility. ? automatic erase before write operation. ? write protect pin for hardware data protection. ? high reliability: typically 1, 000,000 cycles endurance. ? 100 years data retention. ? standard 8-pin pdip/soic/tssop/dfn and 5- pin sot-23/tsot-23 pb-free packages. description the ft24c02a is 2048 bits of serial electric al erasable and programmable read only memory, commonly known as eeprom. they are organized as 256 words of 8 bits (1 byte) each. the devices are fabricated with proprietary advanced cmos pr ocess for low power and low voltage applications. these devices are available in standard 8-lead pdip, 8-lead jedec soic, 8-lead tssop, 8-lead dfn and 5-lead sot-23/tsot-23 packages. a standard 2-wire serial in terface is used to address all read and write functions. our extended v cc range (1.8v to 5.5v) devices enables wide spectrum of applications.
ft24c02a ds3011b-page 2 ? 2009 fremont micro devices inc. pin configuration pin name pin function a2, a1, a0 device address inputs sda serial data input / open drain output scl serial clock input wp write protect vcc power supply gnd ground nc no-connect table 1 all these packaging types come in c onventional or pb-free certified. vcc wp scl sda a2 a1 a0 gnd ft24c02a 1 2 3 4 8 7 6 5 8l dip 8l sop 8l tssop sda wp vcc gnd ft24c02a 2 15 4 sot-23-5 scl 3 8l dfn 8l msop tsot-23-5 figure 1: package types
ft24c02a absolute maximum ratings industrial operating temperature: -40 to 85 storage temperature: -50 to 125 input voltage on any pin relative to ground: -0.3v to v cc + 0.3v maximum voltage: 8v esd protection on all pins: >2000v * stresses exceed those listed under ?absolute maximum rating? may cause permanent damage to the device. functional operation of the device at condit ions beyond those listed in the specification is not guaranteed. prolonged exposure to extreme condition s may affect device reliability or functionality. figure 2: block diagram ? 2009 fremont micro devices inc. ds30 1 1b-page 3
ft24c02a pin descriptions (a) serial clock (scl) the rising edge of this scl input is to latch data into the eeprom device while the falling edge of this clock is to clock data out of the eeprom device. (b) serial data line (sda) sda data line is a bi-directional signal for the serial devices. it is an open drain output signal and can be wired-or with other open-drain output devices. (c) write protect (wp) the ft24c02a devices have a wp pin to protect the whole eeprom array from programming. programming operations are allowed if wp pi n is left un-connected or input to v il . conversely all programming functions are disabled if wp pin is connected to v ih or v cc . read operations is not affected by the wp pin?s input level. memory organization the ft24c02a devices have 16 pages. since eac h page has 16 bytes, random word addressing to ft24c02a will require 8 bits data word addresses. device operation (a) serial clock and data transitions the sda pin is typically pulled to high by an external resistor. data is allowed to change only when serial clock scl is at v il . any sda signal transition may interpret as either a start or stop condition as described below. (b) start condition with scl v ih , a sda transition from high to low is interpreted as a start condition. all valid commands must begin with a start condition. (c) stop condition with scl v ih , a sda transition from low to high is interpreted as a stop condition. all valid read or write commands end with a stop condition. the device goes into the standby mode if it is after a read command. a stop condition after page or byte write command will trigger the chip into the standby mode after the self-timed internal programming finish. (d) acknowledge the 2-wire protocol transmit s address and data to and from the eeprom in 8 bit words. the eeprom acknowledges the data or address by ou tputting a "0" after receiving each word. the acknowledge signal occurs on the 9th serial clock after each word. ds3011b-page 4 ? 2009 fremont micro devices inc.
ft24c02a ? 2009 fremont micro devices inc. ds30 11b-page 5 (e) standby mode the eeprom goes into low power standby mode afte r a fresh power up, after receiving a stop bit in read mode, or after completing a self-time internal programming operation. figure 3: timing diagram for start and stop conditions figure 4: timing diagram for output acknowledge scl sda start condition stop condition data data valid transition scl data in data out start condition a ck
ft24c02a device addressing the 2-wire serial bus protocol mandates an 8 bits device address word after a start bit condition to invoke valid read or write command. the first four mo st significant bits of t he device address must be 1010, which is common to all serial eeprom devices. the nex t three bits are device address bits. these three device address bits (5 th , 6 th and 7 th ) are to match with the external chip select/address pin states. if a match is made, the eeprom device outputs an acknowledge signal after the 8 th read/write bit, otherwise the chip will go into standby mode. however, matching are not be done for ?-5xx? version chips. this three device address bits are not cared and could be coded from 000 (b) to 111 (b). only one ft2 4c02a device can be used on the on 2-wire bus. if a match is made, the eeprom device outputs an acknowledge signal after the 8 th read/write bit, otherwise the chip will go into standby mode. the last or 8 th bit is a read/write command bit. if the 8 th bit is at vih then the chip goes into read mode. if a ?0? is detected, the device enters programming mode. write operations (a) byte write a byte write operation starts when a micro-controlle r sends a start bit condition, follows by a proper eeprom device address and then a write command. if the device addr ess bits match the chip select address, the eeprom device will acknowledge at the 9 th clock cycle. the micro-controller will then send the rest of the lower 8 bits word address. at the 18 th cycle, the eeprom will acknowledge the 8-bit address word. the micro-controller w ill then transmit the 8 bit data. following an acknowldege signal from the eeprom at the 27 th clock cycle, the micr o-controller will issue a stop bit. after receiving the stop bit, the eeprom will go into a self-timed programming mode during which all external inputs will be disabled. after a programming time of t wc , the byte programming will finish and the eeprom dev ice will return to the standby mode. (b) page write a page write is similar to a byte write with the exception that one to sixt een bytes can be programmed along the same page or memory row. all ft24c02 a are organized to have 16 bytes per memory row or page. with the same write command as the byte write, t he micro-controller does not issue a stop bit after sending the 1 st byte data and receiving the acknowledg e signal from the eeprom on the 27 th clock cycle. instead it sends out a second 8-bit data word, with the eeprom acknowledging at the 36 th cycle. this data sending and eeprom acknowle dging cycle repeats unt il the micro-controller sends a stop bit after the n 9 th clock cycle. after which the eeprom device will go into a self- timed partial or full page programming mode. after the page programming completes after a time of t wc , the devices will return to the standby mode. the least significant 4 bits of the word address (c olumn address) increments internally by one after receiving each data word. the rest of the word address bits (row address) do not change internally, but pointing to a specific memory row or page to be programmed. the first page write data word can be of any column address. up to 16 data words can be loaded into a page. if more then 16 data ds3011b-page 6 ? 2009 fremont micro devices inc.
ft24c02a ? 2009 fremont micro devices inc. ds30 11b-page 7 words are loaded, the 17 th data word will be loaded to the 1 st data word column address. the 18 th data word will be loaded to the 2 nd data word column address and so on. in other word, data word address (column address) will ?roll? over the previously loaded data. (c) acknowledge polling acknowledge polling may be used to poll the programming status during a self-timed internal programming. by issuing a valid read or writ e address command, the eepr om will not acknowledge at the 9 th clock cycle if the device is still in the se lf-timed programming mode. however, if the programming completes and the chip has returned to the standby mode, the device will return a valid acknowledge signal at the 9 th clock cycle. read operations the read command is similar to the write command except the 8 th read/write bit in address word is set to ?1?. the three read operation modes are described as follows: (a) current address read the eeprom internal address word counter maintain s the last read or write address plus one if the power supply to the device has not been cut off. to initiate a current address read operation, the micro-controller issues a start bit and a valid device address word with the read/write bit (8 th ) set to ?1?. the eeprom will response with an acknowledge signal on the 9 th serial clock cycle. an 8- bit data word will then be serially clocked out. the internal address word counter will then automatically increase by one. for current addr ess read the micro-controller will not issue an acknowledge signal on the 18 th clock cycle. the micro-controller issues a valid stop bit after the 18 th clock cycle to terminate the read operation. the device then returns to standby mode. (b) sequential read the sequential read is very similar to current addres s read. the micro-controller issues a start bit and a valid device address word with read/write bit (8 th ) set to ?1?. the eeprom will response with an acknowledge signal on the 9 th serial clock cycle. an 8-bi t data word will then be serially clocked out. meanwhile the internally address word counter will then automatically increase by one. unlike current address read, the micro-cont roller sends an acknowledge signal on the 18 th clock cycle signaling the eeprom device that it want s another byte of data. upon receiving the acknowledge signal, the eeprom will serially clocked out an 8-bit data word based on the incremented internal address counter. if the micr o-controller needs another data, it sends out an acknowledge signal on the 27 th clock cycle. another 8-bit data word will then be serially clocked out. this sequential read continues as long as the micro-controller sends an acknowledge signal after receiving a new data word. when the inte rnal address counter reaches its maximum valid address, it rolls over to the beginning of the memo ry array address. similar to current address read, the micro-controller can terminate the sequential read by not acknowledging the last data word received, but sending a stop bit afterwards instead.
ft24c02a ds3011b-page 8 ? 2009 fremont micro devices inc. (c) random read random read is a two-steps process. the first step is to initialize the internal address counter with a target read address using a ?dummy write? instruct ion. the second step is a current address read. to initialize the internal address counter with a target read address, the micro-controller issues a start bit first, follows by a valid device address with the read/write bit (8 th ) set to ?0?. the eeprom will then acknowledge. the micro-controller will then send the address word. again the eeprom will acknowledge. instead of sending a valid wr itten data to the eeprom, the micro-controller performs a current address read instruction to read t he data. note that once a start bit is issued, the eeprom will reset the internal programming pr ocess and continue to exec ute the new instruction - which is to read the current address. *** sda line s t a r t m s b device address l s b r / w a c k w r i t e word address m s b a c k a c k s t o p data l s b figure 5: byte write *** sda line s t a r t m s b device address l s b r / w a c k w r i t e word address(n) m s b a c k a c k a c k l s b s t o p data(n) a c k data(n+x) ... figure 6: page write sda line s t a r t m s b device address l s b r / w a c k r e a d a c k n o a c k s t o p data *** figure 7: current address read
ft24c02a sda line device address r / w a c k r e a d a c k n o a c k s t o p data (n) data (n+1) data (n+2) data (n+3) a c k a c k a c k *** figure 8: sequential read s t a r t m s b device address l s b r / w a c k r e a d a c k n o a s t o p data (n) c k *** s t a r t m s b device address l s b r / w a c k w r i t e word address(n) m s b a c k l s b a c k *** sda line figure 9: random read notes: 1) * = don?t care bits figure 10: scl and sda bus timing ? 2009 fremont micro devices inc. ds30 1 1b-page 9
ft24c02a ac characteristics 1.8 v 2.5-5.0 v symbol parameter min max min max unit f scl clock frequency, scl 400 1000 khz t low clock pulse width low 1.3 0.4 s t high clock pulse width high 0.6 0.4 s t i noise suppression time (1) 180 120 ns t aa clock low to data out valid 0.3 0.9 0.2 0.55 s t buf time the bus must be free before a new transmission can start (1) 1.3 0.5 s t hd.sta start hold time 0.6 0.25 s t su.sta start set-up time 0.6 0.25 s t hd.dat data in hold time 0 0 s t su.dat data in set-up time 100 100 ns t r input rise time (1) 0.3 0.3 s t f input fall time (1) 300 100 ns t su.sto stop set-up time 0.6 0.25 s t dh date out hold time 50 50 ns wr write cycle time 5 5 ms endurance (1) 25 o c, page mode, 3.3v 1,000,000 write cycles notes: 1. this parameter is expected by characterization but is not fully screened by test. 2. ac measurement conditions: r l (connects to vcc): 1.3k ? input pulse voltages: 0.3vcc to 0.7vcc input and output timing reference voltages: 0.5vcc ds3011b-page 10 ? 2009 fremont micro devices inc.
ft24c02a ? 2009 fremont micro devices inc. ds30 11b-page 11 dc characteristics symbol parameter test conditions min typical max unit s v cc1 power supply v cc 1.8 5.5 v i cc supply read current v cc @ 5.0v scl = 400 khz 0.5 1.0 ma i cc supply write current v cc @ 5.0v scl = 400 khz 2.0 3.0 ma i sb1 supply current v cc @ 1.8v, v in = v cc or v ss 1.0 a i sb2 supply current v cc @ 2.5v, v in = v cc or v ss 1.0 a i sb3 supply current v cc @ 5.0v, v in = v cc or v ss 0.07 1.0 a i il input leakage current v in = v cc or v ss 3.0 a i lo output leakage current v in = v cc or v ss 3.0 a v il input low level -0.6 v cc 0.3 v v ih input high level v cc 0.7 v cc + 0.5 v v ol1 output low level v cc @ 1.8v, i ol = 0.15 ma 0.2 v v ol2 output low level v cc @ 3.0v, i ol = 2.1 ma 0.4 v order code: ft24c02a ? xxx - x temperature range u / 5: -40 to 85? package d: dip option g: green package rohs compliant r: rohs compliant packaging b: tube t: tape and reel s: sop m: msop t: tssop n: dfn l: sot23-5 p: tsot23-5
ft24c02a order information order code vcc temperature range package option packaging ft24c02a-5dg-b green package tube ft24c02a-5dr-b rohs tube ft24c02a-udg-b green package tube ft24c02a-udr-b dip8 rohs tube ft24c02a-5sg-b green package tube ft24c02a-5sg-t green package t/r ft24c02a-5sr-b rohs tube ft24c02a-5sr-t rohs t/r ft24c02a-usg-b green package tube ft24c02a-usg-t green package t/r ft24c02a-usr-b rohs tube ft24c02a-usr-t sop8 rohs t/r ft24c02a-utg-b green package tube ft24c02a-utg-t green package t/r ft24c02a-utr-b rohs tube ft24c02a-utr-t tssop8 rohs t/r ft24c02a-5lg-t green package t/r FT24C02A-5LR-T sot23-5 rohs t/r ft24c02a-5pg-t green package t/r ft24c02a-5pr-t tsot23-5 rohs t/r ft24c02a-ung-t green package t/r ft24c02a-unr-t 1.8v-5.5v -40-85 0 c dfn8 rohs t/r ds3011b-page 12 ? 2009 fremont micro devices inc.
ft24c02a ? 2009 fremont micro devices inc. ds30 11b-page 13 dip8 package outline dimensions dimensions in millimeters dimensions in inches symbol min max min max a 3.710 4.310 0.146 0.170 a1 0.510 0.020 a2 3.200 3.600 0.126 0.142 b 0.380 0.570 0.015 0.022 b1 1.524 bsc 0.060 bsc c 0.204 0.360 0.008 0.014 d 9.000 9.400 0.354 0.370 e 6.200 6.600 0.244 0.260 e1 7.320 7.920 0.288 0.312 e 2.540 (bsc) 0.100 bsc l 3.000 3.600 0.118 0.142 e2 8.400 9.000 0.331 0.354
ft24c02a tssop8 package outline dimensions dimensions in millimeters dimensions in inches symbol min max min max d 2.900 3.100 0.114 0.122 e 4.300 4.500 0.169 0.177 b 0.190 0.300 0.007 0.012 c 0.090 0.200 0.004 0.008 e1 6.250 6.550 0.246 0.258 a 1.100 0.043 a2 0.800 1.000 0.031 0.039 a1 0.020 0.150 0.001 0.006 e 0.65 (bsc) 0.026 (bsc) l 0.500 0.700 0.020 0.028 h 0.25 (typ) 0.01 (typ) 1 7 1 7 ds3011b-page 14 ? 2009 fremont micro devices inc.
ft24c02a sop8 package outline dimensions dimensions in millimeters dimensions in inches symbol min max min max a 1.350 1.750 0.053 0.069 a1 0.100 0.250 0.004 0.010 a2 1.350 1.550 0.053 0.061 b 0.330 0.510 0.013 0.020 c 0.170 0.250 0.006 0.010 d 4.700 5.100 0.185 0.200 e 3.800 4.000 0.150 0.157 e1 5.800 6.200 0.228 0.244 e 1.270 (bsc) 0.050 (bsc) l 0.400 1.270 0.016 0.050 0 8 0 8 ? 2009 fremont micro devices inc. ds30 11b-page 15
ft24c02a msop8 package outline dimensions dimensions in millimeters dimensions in inches symbol min max min max a 0.820 1.100 0.320 0.043 a1 0.020 0.150 0.001 0.006 a2 0.750 0.950 0.030 0.037 b 0.250 0.380 0.010 0.015 c 0.090 0.230 0.004 0.009 d 2.900 3.100 0.114 0.122 e 0.65 (bsc) 0.026 (bsc) e 2.900 3.100 0.114 0.122 e1 4.750 5.050 0.187 0.199 l 0.400 0.800 0.016 0.031 0 6 0 6 ds3011b-page 16 ? 2009 fremont micro devices inc.
ft24c02a dfn8 package outline dimensions dimensions in millimeters symbol min nom max a 0.70 0.75 0.80 a1 - 0.02 0.05 b 0.18 0.25 0.03 c 0.18 0.20 0.25 d 1.90 2.00 2.10 d2 1.50ref e 0.50bsc nd 1.50bsc e 2.90 3.00 3.10 e2 1.60ref l 0.30 0.40 0.50 h 0.20 0.25 0.30 l/f surface electroplate ni pdau (nickel, pd, metal) dimension mil 67*75 ? 2009 fremont micro devices inc. ds30 11b-page 17
ft24c02a ds3011b-page 18 ? 2009 fremont micro devices inc. sot-23-5 package outline dimensions dimensions in millimeters dimensions in inches symbol min max min max a 1.050 1.250 0.041 0.049 a1 0.000 0.100 0.000 0.004 a2 1.050 1.150 0.041 0.045 b 0.300 0.500 0.012 0.020 c 0.100 0.200 0.004 0.008 d 2.820 3.020 0.111 0.119 e 1.500 1.700 0.059 0.067 e1 2.650 2.950 0.104 0.116 e 0.95 (bsc) 0.037 (bsc) e1 1.800 2.000 0.071 0.079 l 0.300 0.600 0.012 0.024 ? 0 8 0 6
ft24c02a t sot-23-5 package outline dimensions dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.900 0.028 0.035 a1 0.000 0.100 0.000 0.004 a2 0.700 0.800 0.028 0.031 b 0.350 0.500 0.014 0.020 c 0.080 0.200 0.003 0.008 d 2.820 3.020 0.111 0.119 e 1.600 1.700 0.063 0.067 e1 2.650 2.950 0.104 0.116 e 0.95 (bsc) 0.037 (bsc) e1 1.90 (bsc) 0.075 (bsc) l 0.300 0.600 0.012 0.024 ? 0 8 0 8 ? 2009 fremont micro devices inc. ds30 11b-page 19
ft24c02a appendix a revision history version a: the original datasheet for ft24c02a. * information furnished is believed to be accurate and reliabl e. however, fremont micro devices, incorporated (bvi) assumes no responsibility for the consequences of use of su ch information or for any infringement of patents of other rights of third parties which may result from its us e. no license is granted by implication or otherwise under any patent rights of fremont micro devi ces, incorporated (bvi). specificatio ns mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. fremont micro devices, incorporated (bvi) products are not authorized for use as critical components in life support devices or systems without express written approval of frem ont micro devices, incorporat ed (bvi). the fmd logo is a registered trademark of fremont micro devices, incorporated (bvi). all ot her names are the property of their respective owners. ds3011b-page 20 ? 2009 fremont micro devices inc.

▲Up To Search▲

Price & Availability of FT24C02A-5LR-T

	To Download FT24C02A-5LR-T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .